I had previously posted a brief summary of our ISCA 2011 paper. The basic idea was to design a 3D stack of memory chips and one special interface chip, connected with TSVs (through silicon vias). We argue that the interface chip should have photonic components and memory scheduling logic. The use of such a stack enables game-changing optimizations (photonic access, scalable scheduling) without disrupting the manufacture of commodity memory chips.
When we presented our work at Micron recently (see related post by Ani Udipi), we were told that Micron has a full silicon prototype that incorporates some of these concepts. We were very excited to hear that a 3D stacked memory/logic organization similar to our proposal is implementable and could be reality in the near future. Slide 17 of the report from the Micron Winter Analyst Conference, February 2011, describes Micron's Hybrid Memory Cube (HMC, Figure reproduced below). The HMC has a Micron-designed logic controller at the bottom of the stack (what we dub as the interface chip in our work) and it is connected to multiple DRAM chips with TSVs. Details of what is on the logic controller have not been released yet. Micron is partnering with Open-Silicon to take advantage of the opportunities made possible by the HMC.
This is an exciting development and I expect that one could discover many creative ways to put useful functionality on the interface chip. Prior work has proposed several ways to add functionality to DRAM chips: row buffer caches, processing in memory, error correction features, photonic components, etc. Many of these ideas were unimplementable because of their impact on cost, but they may be worth attempting in the context of a 3D memory stack. This is also an opportunity to add value to memory products, an especially important consideration as density growth flattens or as we move to new memory technologies that have varying maintenance needs.
While most prior academic work on 3D architecture has been processor-centric, the potential benefit of memory-centric 3D stacking is relatively unexplored. This is in spite of the fact that memory companies have embraced 3D stacking much more than processor companies. 3D memory chip stacks are currently manufactured in various forms by Tezzaron, Samsung, and Elpida among others. The concept of building a single chip and then reusing it within 3D chip stacks to create multiple different products has been proposed previously for processors (papers from UCSB and Utah). Given the economic impact of this concept, the cost-sensitive memory industry stands to gain more from it. Memory companies operate at very small margins. They therefore strive to optimize cost-per-bit and almost exclusively design for high volumes. They are averse to adding any feature that will increase cost for millions of chips, but will only be used by a small market segment. But with 3D chip stacks, the same high-volume commodity DRAM chip can be bonded to different interface chips to create different products for each market segment. This may well emerge as the most compelling application of 3D stacking within the high performance domain.
When we presented our work at Micron recently (see related post by Ani Udipi), we were told that Micron has a full silicon prototype that incorporates some of these concepts. We were very excited to hear that a 3D stacked memory/logic organization similar to our proposal is implementable and could be reality in the near future. Slide 17 of the report from the Micron Winter Analyst Conference, February 2011, describes Micron's Hybrid Memory Cube (HMC, Figure reproduced below). The HMC has a Micron-designed logic controller at the bottom of the stack (what we dub as the interface chip in our work) and it is connected to multiple DRAM chips with TSVs. Details of what is on the logic controller have not been released yet. Micron is partnering with Open-Silicon to take advantage of the opportunities made possible by the HMC.
This is an exciting development and I expect that one could discover many creative ways to put useful functionality on the interface chip. Prior work has proposed several ways to add functionality to DRAM chips: row buffer caches, processing in memory, error correction features, photonic components, etc. Many of these ideas were unimplementable because of their impact on cost, but they may be worth attempting in the context of a 3D memory stack. This is also an opportunity to add value to memory products, an especially important consideration as density growth flattens or as we move to new memory technologies that have varying maintenance needs.
While most prior academic work on 3D architecture has been processor-centric, the potential benefit of memory-centric 3D stacking is relatively unexplored. This is in spite of the fact that memory companies have embraced 3D stacking much more than processor companies. 3D memory chip stacks are currently manufactured in various forms by Tezzaron, Samsung, and Elpida among others. The concept of building a single chip and then reusing it within 3D chip stacks to create multiple different products has been proposed previously for processors (papers from UCSB and Utah). Given the economic impact of this concept, the cost-sensitive memory industry stands to gain more from it. Memory companies operate at very small margins. They therefore strive to optimize cost-per-bit and almost exclusively design for high volumes. They are averse to adding any feature that will increase cost for millions of chips, but will only be used by a small market segment. But with 3D chip stacks, the same high-volume commodity DRAM chip can be bonded to different interface chips to create different products for each market segment. This may well emerge as the most compelling application of 3D stacking within the high performance domain.
