Warning: This post may contain some shameless advertizing for our upcoming ISCA paper. :-)
Based on a reviewer suggestion, we are changing the title of our recently accepted ISCA paper from
"Designing a Terascale Memory Node for Future Exascale Systems"
"Combining Memory and a Controller with Photonics through 3D-Stacking to
Enable Scalable and Energy-Efficient Systems"
Believe me, it took many iterations to find something that was descriptive, accurate, and marginally pleasant-sounding :-). While throwing in every buzzword makes for a clunky title, such titles are essential for flagging the attention of the right audience (those working on photonics, 3D, and memory systems).
I mention the following example of a bad title to my students. Our ISCA 2001 paper was on runahead execution (a form of hardware prefetching) and appeared with three other papers in the same conference on the same topic. Our non-descriptive title said: "Dynamically Allocating Processor Resources between Nearby and Distant ILP". There's little in the title to indicate that it is about runahead. As a result, our paper got left out of most subsequent runahead conversations and had minimal impact. In terms of citations (the closest quantitative measure of impact), our paper has 70+ citations; each of the other three have 200+. I might have felt robbed if the paper was actually earth-shattering; in retrospect, the design was quite unimplementable (and that may no doubt have contributed to its low impact). In my view, Onur Mutlu's subsequent thesis work put forth a far more elegant runahead execution design and made most prior work obsolete.
For those interested, here's an executive summary of our ISCA'11 work (done jointly with HP Labs). The killer app for photonics is its high bandwidth in and out of a chip (something we can't do for long with electrical pins). However, introducing photonic components into a cost-sensitive DRAM chip can be highly disruptive. We take advantage of the fact that industry is possibly moving towards 3D-stacked DRAM chip packages and introduce a special interface die on the DRAM stack. The interface die has photonic components and some memory controller functionality. By doing this, we use photonics to break the pin barrier, but do not disrupt the manufacture of commodity DRAM chips. For communication within the 3D stack, we compute an energy-optimal design point (exactly how much of the intra-stack communication should happen with optics and how much with electrical wiring). It turns out that there is no need for optics to penetrate into the DRAM dies themselves. We also define a novel protocol to schedule memory operations in a scalable manner: the on-chip memory controller does minimal book-keeping and simply reserves a speculative slot on the photonic bus for the data return. Most scheduling minutiae are handled by the logic on the DRAM stack's interface die.