Five years ago, our group had visited Micron for informal research discussions (documented in an
earlier blog post). It is fair to say that we were generally discouraged from messing with memory chips, and instead encouraged to look at innovations outside the memory chip. We were advised (warned) that even introducing a 0.5% area overhead to a memory chip would be untenable. And this was the dominant view within the memory industry. Many academic reviewers over the years have provided similar advice.
As is now evident, that advice was mis-guided.
Just as there are markets for a variety of processor chips, there also are emerging markets for a variety of memory devices. Some memory devices will incur a cost penalty in order to provide lower latency or lower energy. For example, see the slide below that was presented by Hynix at an
ISCA 2016 keynote, arguing for a memory chip that offers 30% lower latency, while incurring a 28% area overhead.
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| From the ISCA 2016 keynote talk by Seok-Hee Lee (SK Hynix) |
Micron's
Hybrid Memory Cube is also designed with many small DRAM arrays that reduce "overfetch" but occupy more area. This was the key idea in our
ISCA 2010 paper -- an idea that received a lot of criticism from reviewers (at least one "Strong Reject"), ISCA attendees (at least one nasty question during the Q&A), and designers at Micron (the ominous reality check on area overheads).
Hopefully, program committees will no longer cite the "cost-sensitive memory industry" to reject otherwise good papers. Market forces are constantly evolving -- they should ideally not come in the way of a strong technical argument.
